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altera corporation 1 max 7000 programmable logic device family december 2002, ver. 6.5 data sheet ds-max7000-6.5 features... high-performance, eeprom-based programmable logic devices (plds) based on second-generation max ? architecture 5.0-v in-system programmability (isp) through the built-in ieee std. 1149.1 joint test action group (jtag) interface available in max 7000s devices ? isp circuitry compatible with ieee std. 1532 includes 5.0-v max 7000 devices and 5.0-v isp-based max 7000s devices built-in jtag boundary-scan test (bst) circuitry in max 7000s devices with 128 or more macrocells complete epld family with logic densities ranging from 600 to 5,000 usable gates (see tables 1 and 2 ) 5-ns pin-to-pin logic delays with up to 175.4-mhz counter frequencies (including interconnect) pci-compliant devices available f for information on in-system programmable 3.3-v max 7000a or 2.5-v max 7000b devices, see the max 7000a programmable logic device family data sheet or the max 7000b programmable logic device family data sheet . table 1. max 7000 device features feature epm7032 epm7064 epm7096 epm7128e epm7160e epm7192e epm7256e usable gates 600 1,250 1,800 2,500 3,200 3,750 5,000 macrocells 32 64 96 128 160 192 256 logic array blocks 2468101216 maximum user i/o pins 36 68 76 100 104 124 164 t pd (ns) 6 6 7.5 7.5 10 12 12 t su (ns)5566777 t fsu (ns)2.5 2.533333 t co1 (ns)444.54.5566 f cnt (mhz) 151.5 151.5 125.0 125.0 100.0 90.9 90.9
2 altera corporation max 7000 programmable logic device family data sheet ...and more features open-drain output option in max 7000s devices programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls programmable power-saving mode for a reduction of over 50 % in each macrocell configurable expander product-term distribution, allowing up to 32 product terms per macrocell 44 to 208 pins available in plastic j-lead chip carrier (plcc), ceramic pin-grid array (pga), plastic quad flat pack (pqfp), power quad flat pack (rqfp), and 1.0-mm thin quad flat pack (tqfp) packages programmable security bit for protection of proprietary designs 3.3-v or 5.0-v operation ? multivolt tm i/o interface operation, allowing devices to interface with 3.3-v or 5.0-v devices (multivolt i/o operation is not available in 44-pin packages) ? pin compatible with low-voltage max 7000a and max 7000b devices enhanced features available in max 7000e and max 7000s devices ? six pin- or logic-driven output enable signals ? two global clock signals with optional inversion ? enhanced interconnect resources for improved routability ? fast input setup times provided by a dedicated path from i/o pin to macrocell registers ? programmable output slew-rate control software design support and automatic place-and-route provided by altera?s development system for windows-based pcs and sun sparcstation, and hp 9000 series 700/800 workstations table 2. max 7000s device features feature epm7032s epm7064s epm7128s epm7160s epm7192s epm7256s usable gates 600 1,250 2,500 3,200 3,750 5,000 macrocells 32 64 128 160 192 256 logic array blocks 2 4 8 10 12 16 maximum user i/o pins 36 68 100 104 124 164 t pd (ns)55667.57.5 t su (ns) 2.9 2.9 3.4 3.4 4.1 3.9 t fsu (ns) 2.5 2.5 2.5 2.5 3 3 t co1 (ns) 3.2 3.2 4 3.9 4.7 4.7 f cnt (mhz) 175.4 175.4 147.1 149.3 125.0 128.2
altera corporation 3 max 7000 programmable logic device family data sheet additional design entry and simulation support provided by edif 2 0 0 and 3 0 0 netlist files, library of parameterized modules (lpm), verilog hdl, vhdl, and other interfaces to popular eda tools from manufacturers such as cadence, exemplar logic, mentor graphics, orcad, synopsys, and veribest programming support ? altera?s master programming unit (mpu) and programming hardware from third-party manufacturers program all max 7000 devices ?the bitblaster tm serial download cable, byteblastermv tm parallel port download cable, and masterblaster tm serial/universal serial bus (usb) download cable program max 7000s devices general description the max 7000 family of high-density, high-performance plds is based on altera?s second-generation max architecture. fabricated with advanced cmos technology, the eeprom-based max 7000 family provides 600 to 5,000 usable gates, isp, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 mhz. max 7000s devices in the -5, -6, -7, and -10 speed grades as well as max 7000 and max 7000e devices in -5, -6, -7, -10p, and -12p speed grades comply with the pci special interest group (pci sig) pci local bus specification , revision 2.2 . see table 3 for available speed grades. table 3. max 7000 speed grades device speed grade -5 -6 -7 -10p -10 -12p -12 -15 -15t -20 epm7032 vv v vvv epm7032s vvv v epm7064 vvvvv epm7064s vvv v epm7096 vvvv epm7128e vvvvvv epm7128s vv v v epm7160e vv vv v epm7160s vv v v epm7192e vvv v epm7192s vv v epm7256e vvv v epm7256s vv v
4 altera corporation max 7000 programmable logic device family data sheet the max 7000e devices?including the epm7128e, epm7160e, epm7192e, and epm7256e devices?have several enhanced features: additional global clocking, additional output enable controls, enhanced interconnect resources, fast input registers, and a programmable slew rate. in-system programmable max 7000 devices?called max 7000s devices?include the epm7032s, epm7064s, epm7128s, epm7160s, epm7192s, and epm7256s devices. max 7000s devices have the enhanced features of max 7000e devices as well as jtag bst circuitry in devices with 128 or more macrocells, isp, and an open-drain output option. see table 4 . notes: (1) available only in epm7128s, epm7160s, epm7192s, and epm7256s devices only. (2) the multivolt i/o interface is not available in 44-pin packages. table 4. max 7000 device features feature epm7032 epm7064 epm7096 all max 7000e devices all max 7000s devices isp via jtag interface v jtag bst circuitry v (1) open-drain output option v fast input registers vv six global output enables vv two global clocks vv slew-rate control vv multivolt interface (2) vvv programmable register vvv parallel expanders vvv shared expanders vvv power-saving mode vvv security bit vvv pci-compliant devices available vvv
altera corporation 5 max 7000 programmable logic device family data sheet the max 7000 architecture supports 100 % ttl emulation and high-density integration of ssi, msi, and lsi logic functions. the max 7000 architecture easily integrates multiple devices ranging from pals, gals, and 22v10s to mach and plsi devices. max 7000 devices are available in a wide range of packages, including plcc, pga, pqfp, rqfp, and tqfp packages. see table 5 . notes: (1) when the jtag interface in max 7000s devices is used for either boundary-scan testing or for isp, four i/o pins become jtag pins. (2) perform a complete thermal analysis before committing a design to this device package. for more information, see the operating requirements for altera devices data sheet . max 7000 devices use cmos eeprom cells to implement logic functions. the user-configurable max 7000 architecture accommodates a variety of independent combinatorial and sequential logic functions. the devices can be reprogrammed for quick and efficient iterations during design development and debug cycles, and can be programmed and erased up to 100 times. table 5. max 7000 maximum user i/o pins note (1) device 44- pin plcc 44- pin pqfp 44- pin tqfp 68- pin plcc 84- pin plcc 100- pin pqfp 100- pin tqfp 160- pin pqfp 160- pin pga 192- pin pga 208- pin pqfp 208- pin rqfp epm7032 36 36 36 epm7032s 36 36 epm7064 36 36 52 68 68 epm7064s 36 36 68 68 epm7096 52 64 76 epm7128e 68 84 100 epm7128s 68 84 84 (2) 100 epm7160e 64 84 104 epm7160s 64 84 (2) 104 epm7192e 124 124 epm7192s 124 epm7256e 132 (2) 164 164 epm7256s 164 (2) 164
6 altera corporation max 7000 programmable logic device family data sheet max 7000 devices contain from 32 to 256 macrocells that are combined into groups of 16 macrocells, called logic array blocks (labs). each macrocell has a programmable- and /fixed- or array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. to build complex logic functions, each macrocell can be supplemented with both shareable expander product terms and high- speed parallel expander product terms to provide up to 32 product terms per macrocell. the max 7000 family provides programmable speed/power optimization. speed-critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. this speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50 % or lower power while adding only a nominal timing delay. max 7000e and max 7000s devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non-speed-critical signals are switching. the output drivers of all max 7000 devices (except 44-pin devices) can be set for either 3.3-v or 5.0-v operation, allowing max 7000 devices to be used in mixed-voltage systems. the max 7000 family is supported byaltera development systems, which are integrated packages that offer schematic, text?including vhdl, verilog hdl, and the altera hardware description language (ahdl)? and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. the software provides edif 2 0 0 and 3 0 0, lpm, vhdl, verilog hdl, and other interfaces for additional design entry and simulation support from other industry- standard pc- and unix-workstation-based eda tools. the software runs on windows-based pcs, as well as sun sparcstation, and hp 9000 series 700/800 workstations. f for more information on development tools, see the max+plus ii programmable logic development system & software data sheet and the quartus programmable logic development system & software data sheet . functional description the max 7000 architecture includes the following elements: logic array blocks macrocells expander product terms (shareable and parallel) programmable interconnect array i/o control blocks
altera corporation 7 max 7000 programmable logic device family data sheet the max 7000 architecture includes four dedicated inputs that can be used as general-purpose inputs or as high-speed, global control signals (clock, clear, and two output enable signals) for each macrocell and i/o pin. figure 1 shows the architecture of epm7032, epm7064, and epm7096 devices. figure 1. epm7032, epm7064 & epm7096 device block diagram i/o control block 8 to 16 i/o pins 8 to 16 8 to 16 16 36 i/o control block 8 to 16 8 to 16 i/o pins 36 8 to 16 16 8 to 16 8 to 16 i/o pins 36 8 to 16 16 i/o control block i/o control block 8 to 16 i/o pins 8 to 16 8 to 16 16 36 lab a lab b lab c macrocells 33 to 48 lab d input/gclrn input/oe1 input/oe2 macrocells 17 to 32 macrocells 49 to 64 pia input/glck1 macrocells 1 to 16
8 altera corporation max 7000 programmable logic device family data sheet figure 2 shows the architecture of max 7000e and max 7000s devices. figure 2. max 7000e & max 7000s device block diagram logic array blocks the max 7000 device architecture is based on the linking of high- performance, flexible, logic array modules called logic array blocks (labs). labs consist of 16-macrocell arrays, as shown in figures 1 and 2 . multiple labs are linked together via the programmable interconnect array (pia), a global bus that is fed by all dedicated inputs, i/o pins, and macrocells. 6 6 input/gclrn 6 output enables 6 output enables 16 36 36 16 i/o control block lab c lab d i/o control block 6 16 36 36 16 i/o control block lab a lab b i/o control block 6 6 to16 input/gclk1 i nput/oe2/gclk2 input/oe1 6 to 16 i/o pins 6 to 16 i/o pins 6 to 16 i/o pin s 6 to 16 i/o pin s 6 to16 6 to16 6 to16 6 to16 6 to16 6 to16 6 to16 6 to16 6 to16 6 to16 6 to16 macrocells 1 to 16 macrocells 17 to 32 macrocells 33 to 48 macrocells 49 to 64 pia
altera corporation 9 max 7000 programmable logic device family data sheet each lab is fed by the following signals: 36 signals from the pia that are used for general logic inputs global controls that are used for secondary register functions direct input paths from i/o pins to the registers that are used for fast setup times for max 7000e and max 7000s devices macrocells the max 7000 macrocell can be individually configured for either sequential or combinatorial logic operation. the macrocell consists of three functional blocks: the logic array, the product-term select matrix, and the programmable register. the macrocell of epm7032, epm7064, and epm7096 devices is shown in figure 3 . figure 3. epm7032, epm7064 & epm7096 device macrocell product - t er t t m s elect m atri x 36 s ignals f rom pia 16 expander product t er t t ms logic arra y p a rallel lo g ic expanders ( from other macrocells ) s hared lo g ic expanders clear select global clear global clocks clock/ enable select 2 prn clrn d/t q ena register bypass to i/o control block to pia programmable register from i/o pin fast input select vcc
10 altera corporation max 7000 programmable logic device family data sheet figure 4 shows a max 7000e and max 7000s device macrocell. figure 4. max 7000e & max 7000s device macrocell combinatorial logic is implemented in the logic array, which provides five product terms per macrocell. the product-term select matrix allocates these product terms for use as either primary logic inputs (to the or and xor gates) to implement combinatorial functions, or as secondary inputs to the macrocell?s register clear, preset, clock, and clock enable control functions. two kinds of expander product terms (?expanders?) are available to supplement macrocell logic resources: shareable expanders, which are inverted product terms that are fed back into the logic array parallel expanders, which are product terms borrowed from adjacent macrocells the altera development system automatically optimizes product-term allocation according to the logic requirements of the design. for registered functions, each macrocell flipflop can be individually programmed to implement d, t, jk, or sr operation with programmable clock control. the flipflop can be bypassed for combinatorial operation. during design entry, the designer specifies the desired flipflop type; the altera development software then selects the most efficient flipflop operation for each registered function to optimize resource utilization. product- te r m select matrix 36 signals from pia 16 expander product terms logic array parallel logic expanders (from other macrocells) shared logic expanders clear select global clear global clocks clock/ enable select 2 prn clrn d/t q ena register bypass to i/o control block to pia programmable register from i/o pin fast input select vcc
altera corporation 11 max 7000 programmable logic device family data sheet each programmable register can be clocked in three different modes: by a global clock signal. this mode achieves the fastest clock-to- output performance. by a global clock signal and enabled by an active-high clock enable. this mode provides an enable on each flipflop while still achieving the fast clock-to-output performance of the global clock. by an array clock implemented with a product term. in this mode, the flipflop can be clocked by signals from buried macrocells or i/o pins. in epm7032, epm7064, and epm7096 devices, the global clock signal is available from a dedicated clock pin, gclk1 , as shown in figure 1 . in max 7000e and max 7000s devices, two global clock signals are available. as shown in figure 2 , these global clock signals can be the true or the complement of either of the global clock pins, gclk1 or gclk2 . each register also supports asynchronous preset and clear functions. as shown in figures 3 and 4 , the product-term select matrix allocates product terms to control these operations. although the product-term-driven preset and clear of the register are active high, active-low control can be obtained by inverting the signal within the logic array. in addition, each register clear function can be individually driven by the active-low dedicated global clear pin ( gclrn ). upon power-up, each register in the device will be set to a low state. all max 7000e and max 7000s i/o pins have a fast input path to a macrocell register. this dedicated path allows a signal to bypass the pia and combinatorial logic and be driven to an input d flipflop with an extremely fast (2.5 ns) input setup time. expander product terms although most logic functions can be implemented with the five product terms available in each macrocell, the more complex logic functions require additional product terms. another macrocell can be used to supply the required logic resources; however, the max 7000 architecture also allows both shareable and parallel expander product terms (?expanders?) that provide additional product terms directly to any macrocell in the same lab. these expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain the fastest possible speed.
12 altera corporation max 7000 programmable logic device family data sheet shareable expanders each lab has 16 shareable expanders that can be viewed as a pool of uncommitted single product terms (one from each macrocell) with inverted outputs that feed back into the logic array. each shareable expander can be used and shared by any or all macrocells in the lab to build complex logic functions. a small delay ( t sexp ) is incurred when shareable expanders are used. figure 5 shows how shareable expanders can feed multiple macrocells. figure 5. shareable expanders shareable expanders can be shared by any or all macrocells in an lab. parallel expanders parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. parallel expanders allow up to 20 product terms to directly feed the macrocell or logic, with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the lab. macrocell product-ter m logic product-term select matrix macrocell product-ter m logic 36 signals from pia 16 shared expanders
altera corporation 13 max 7000 programmable logic device family data sheet the compiler can allocate up to three sets of up to five parallel expanders automatically to the macrocells that require additional product terms. each set of five parallel expanders incurs a small, incremental timing delay ( t pexp ). for example, if a macrocell requires 14 product terms, the compiler uses the five dedicated product terms within the macrocell and allocates two sets of parallel expanders; the first set includes five product terms and the second set includes four product terms, increasing the total delay by 2 t pexp . two groups of 8 macrocells within each lab (e.g., macrocells 1 through 8 and 9 through 16) form two chains to lend or borrow parallel expanders. a macrocell borrows parallel expanders from lower- numbered macrocells. for example, macrocell 8 can borrow parallel expanders from macrocell 7, from macrocells 7 and 6, or from macrocells 7, 6, and 5. within each group of 8, the lowest-numbered macrocell can only lend parallel expanders and the highest-numbered macrocell can only borrow them. figure 6 shows how parallel expanders can be borrowed from a neighboring macrocell. figure 6. parallel expanders unused product terms in a macrocell can be allocated to a neighboring macrocell. preset clock clear product- te r m select matrix preset clock clear product- te r m select matrix macrocell product- term logic from previous macrocell to next macrocell macrocell product- term logic 36 signals from pia 16 shared expanders
14 altera corporation max 7000 programmable logic device family data sheet programmable interconnect array logic is routed between labs via the programmable interconnect array (pia). this global bus is a programmable path that connects any signal source to any destination on the device. all max 7000 dedicated inputs, i/o pins, and macrocell outputs feed the pia, which makes the signals available throughout the entire device. only the signals required by each lab are actually routed from the pia into the lab. figure 7 shows how the pia signals are routed into the lab. an eeprom cell controls one input to a 2-input and gate, which selects a pia signal to drive into the lab. figure 7. pia routing while the routing delays of channel-based routing schemes in masked or fpgas are cumulative, variable, and path-dependent, the max 7000 pia has a fixed delay. the pia thus eliminates skew between signals and makes timing performance easy to predict. i/o control blocks the i/o control block allows each i/o pin to be individually configured for input, output, or bidirectional operation. all i/o pins have a tri-state buffer that is individually controlled by one of the global output enable signals or directly connected to ground or v cc . figure 8 shows the i/o control block for the max 7000 family. the i/o control block of epm7032, epm7064, and epm7096 devices has two global output enable signals that are driven by two dedicated active-low output enable pins ( oe1 and oe2 ). the i/o control block of max 7000e and max 7000s devices has six global output enable signals that are driven by the true or complement of two output enable signals, a subset of the i/o pins, or a subset of the i/o macrocells. to lab pia signals
altera corporation 15 max 7000 programmable logic device family data sheet figure 8. i/o control block of max 7000 devices note: (1) the open-drain output option is available only in max 7000s devices. e pm7032, epm7064 & epm7096 devices m ax 7000e & max 7000s devices to pia gnd vcc f rom macrocell oe1 oe2 from macrocell fast input to macrocell register slew-rate control to pia to other i/o pins six global output enable signals pia gnd vcc open-drain output (1)
16 altera corporation max 7000 programmable logic device family data sheet when the tri-state buffer control is connected to ground, the output is tri-stated (high impedance) and the i/o pin can be used as a dedicated input. when the tri-state buffer control is connected to v cc , the output is enabled. the max 7000 architecture provides dual i/o feedback, in which macrocell and pin feedbacks are independent. when an i/o pin is configured as an input, the associated macrocell can be used for buried logic. in-system programma- bility (isp) max 7000s devices are in-system programmable via an industry-standard 4-pin joint test action group (jtag) interface (ieee std. 1149.1-1990). isp allows quick, efficient iterations during design development and debugging cycles. the max 7000s architecture internally generates the high programming voltage required to program eeprom cells, allowing in-system programming with only a single 5.0 v power supply. during in-system programming, the i/o pins are tri-stated and pulled-up to eliminate board conflicts. the pull-up value is nominally 50 k?. isp simplifies the manufacturing flow by allowing devices to be mounted on a printed circuit board with standard in-circuit test equipment before they are programmed. max 7000s devices can be programmed by downloading the information via in-circuit testers (ict), embedded processors, or the altera masterblaster, byteblastermv, byteblaster, bitblaster download cables. (the byteblaster cable is obsolete and is replaced by the byteblastermv cable, which can program and configure 2.5-v, 3.3-v, and 5.0-v devices.) programming the devices after they are placed on the board eliminates lead damage on high-pin-count packages (e.g., qfp packages) due to device handling and allows devices to be reprogrammed after a system has already shipped to the field. for example, product upgrades can be performed in the field via software or modem. in-system programming can be accomplished with either an adaptive or constant algorithm. an adaptive algorithm reads information from the unit and adapts subsequent programming steps to achieve the fastest possible programming time for that unit. because some in-circuit testers cannot support an adaptive algorithm, altera offers devices tested with a constant algorithm. devices tested to the constant algorithm have an ?f? suffix in the ordering code. the jam tm standard test and programming language (stapl) can be used to program max 7000s devices with in-circuit testers, pcs, or embedded processor.
altera corporation 17 max 7000 programmable logic device family data sheet f for more information on using the jam language, see application note 88 (using the jam language for isp & icr via an embedded processor) . the isp circuitry in max 7000s devices is compatible with ieee std. 1532 specification. the ieee std. 1532 is a standard developed to allow concurrent isp between multiple pld vendors. programmable speed/power control max 7000 devices offer a power-saving mode that supports low-power operation across user-defined signal paths or the entire device. this feature allows total power dissipation to be reduced by 50 % or more, because most logic applications require only a small fraction of all gates to operate at maximum frequency. the designer can program each individual macrocell in a max 7000 device for either high-speed (i.e., with the turbo bit tm option turned on) or low-power (i.e., with the turbo bit option turned off) operation. as a result, speed-critical paths in the design can run at high speed, while the remaining paths can operate at reduced power. macrocells that run at low power incur a nominal timing delay adder ( t lpa ) for the t lad , t lac , t ic , t en , and t sexp , t acl , and t cppw parameters. output configuration max 7000 device outputs can be programmed to meet a variety of system-level requirements. multivolt i/o interface max 7000 devices?except 44-pin devices?support the multivolt i/o interface feature, which allows max 7000 devices to interface with systems that have differing supply voltages. the 5.0-v devices in all packages can be set for 3.3-v or 5.0-v i/o pin operation. these devices have one set of vcc pins for internal operation and input buffers ( vccint ), and another set for i/o output drivers ( vccio ). the vccint pins must always be connected to a 5.0-v power supply. with a 5.0-v v ccint level, input voltage thresholds are at ttl levels, and are therefore compatible with both 3.3-v and 5.0-v inputs. the vccio pins can be connected to either a 3.3-v or a 5.0-v power supply, depending on the output requirements. when the vccio pins are connected to a 5.0-v supply, the output levels are compatible with 5.0-v systems. when v ccio is connected to a 3.3-v supply, the output high is 3.3 v and is therefore compatible with 3.3-v or 5.0-v systems. devices operating with v ccio levels lower than 4.75 v incur a nominally greater timing delay of t od2 instead of t od1 .
18 altera corporation max 7000 programmable logic device family data sheet open-drain output option (max 7000s devices only) max 7000s devices provide an optional open-drain (functionally equivalent to open-collector) output for each i/o pin. this open-drain output enables the device to provide system-level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. it can also provide an additional wired- or plane. by using an external 5.0-v pull-up resistor, output pins on max 7000s devices can be set to meet 5.0-v cmos input voltages. when v ccio is 3.3 v, setting the open drain option will turn off the output pull-up transistor, allowing the external pull-up resistor to pull the output high enough to meet 5.0-v cmos input voltages. when v ccio is 5.0 v, setting the output drain option is not necessary because the pull-up transistor will already turn off when the pin exceeds approximately 3.8 v, allowing the external pull-up resistor to pull the output high enough to meet 5.0-v cmos input voltages. slew-rate control the output buffer for each max 7000e and max 7000s i/o pin has an adjustable output slew rate that can be configured for low-noise or high- speed performance. a faster slew rate provides high-speed transitions for high-performance systems. however, these fast transitions may introduce noise transients into the system. a slow slew rate reduces system noise, but adds a nominal delay of 4 to 5 ns. in max 7000e devices, when the turbo bit is turned off, the slew rate is set for low noise performance. for max 7000s devices, each i/o pin has an individual eeprom bit that controls the slew rate, allowing designers to specify the slew rate on a pin-by-pin basis. programming with external hardware max 7000 devices can be programmed on windows-based pcs with the altera logic programmer card, the master programming unit (mpu), and the appropriate device adapter. the mpu performs a continuity check to ensure adequate electrical contact between the adapter and the device. f for more information, see the altera programming hardware data sheet . the altera development system can use text- or waveform-format test vectors created with the text editor or waveform editor to test the programmed device. for added design verification, designers can perform functional testing to compare the functional behavior of a max 7000 device with the results of simulation. moreover, data i/o, bp microsystems, and other programming hardware manufacturers also provide programming support for altera devices. f for more information, see the programming hardware manufacturers .
altera corporation 19 max 7000 programmable logic device family data sheet ieee std. 1149.1 (jtag) boundary-scan support max 7000 devices support jtag bst circuitry as specified by ieee std. 1149.1-1990. table 6 describes the jtag instructions supported by the max 7000 family. the pin-out tables (see the altera web site ( http://www.altera.com ) or the altera digital library for pin-out information) show the location of the jtag control pins for each device. if the jtag interface is not required, the jtag pins are available as user i/o pins. table 6. max 7000 jtag instructions jtag instruction devices description sample/preload epm7128s epm7160s epm7192s epm7256s allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern output at the device pins. extest epm7128s epm7160s epm7192s epm7256s allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. bypass epm7032s epm7064s epm7128s epm7160s epm7192s epm7256s places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through a selected device to adjacent devices during normal device operation. idcode epm7032s epm7064s epm7128s epm7160s epm7192s epm7256s selects the idcode register and places it between tdi and tdo , allowing the idcode to be serially shifted out of tdo . isp instructions epm7032s epm7064s epm7128s epm7160s epm7192s epm7256s these instructions are used when programming max 7000s devices via the jtag ports with the masterblaster, byteblastermv, bitblaster download cable, or using a jam file ( .jam ), jam byte-code file ( .jbc ), or serial vector format file ( .svf ) via an embedded processor or test equipment.
20 altera corporation max 7000 programmable logic device family data sheet the instruction register length of max 7000s devices is 10 bits. tables 7 and 8 show the boundary-scan register length and device idcode information for max 7000s devices. note: (1) this device does not support jtag boundary-scan testing. selecting either the extest or sample/preload instruction will select the one-bit bypass register. notes: (1) the most significant bit (msb) is on the left. (2) the least significant bit (lsb) for all jtag idcodes is 1 . table 7. max 7000s boundary-scan register length device boundary-scan register length epm7032s 1 (1) epm7064s 1 (1) epm7128s 288 epm7160s 312 epm7192s 360 epm7256s 480 table 8. 32-bit max 7000 device idcode note (1) device idcode (32 bits) version (4 bits) part number (16 bits) manufacturer?s identity (11 bits) 1 (1 bit) (2) epm7032s 0000 0111 0000 0011 0010 00001101110 1 epm7064s 0000 0111 0000 0110 0100 00001101110 1 epm7128s 0000 0111 0001 0010 1000 00001101110 1 epm7160s 0000 0111 0001 0110 0000 00001101110 1 epm7192s 0000 0111 0001 1001 0010 00001101110 1 epm7256s 0000 0111 0010 0101 0110 00001101110 1
altera corporation 21 max 7000 programmable logic device family data sheet figure 9 shows the timing requirements for the jtag signals. figure 9. max 7000 jtag waveforms table 9 shows the jtag timing parameters and values for max 7000s devices. t do t ck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi t ms g nal o be u red g nal o be iven t jszx t jssu t jsh t jsco t jsxz table 9. jtag timing parameters & values for max 7000s devices symbol parameter min max unit t jcp tck clock period 100 ns t jch tck clock high time 50 ns t jcl tck clock low time 50 ns t jpsu jtag port setup time 20 ns t jph jtag port hold time 45 ns t jpco jtag port clock to output 25 ns t jpzx jtag port high impedance to valid output 25 ns t jpxz jtag port valid output to high impedance 25 ns t jssu capture register setup time 20 ns t jsh capture register hold time 45 ns t jsco update register clock to output 25 ns t jszx update register high impedance to valid output 25 ns t jsxz update register valid output to high impedance 25 ns
22 altera corporation max 7000 programmable logic device family data sheet f for more information, see application note 39 (ieee 1149.1 (jtag) boundary-scan testing in altera devices) . design security all max 7000 devices contain a programmable security bit that controls access to the data programmed into the device. when this bit is programmed, a proprietary design implemented in the device cannot be copied or retrieved. this feature provides a high level of design security because programmed data within eeprom cells is invisible. the security bit that controls this function, as well as all other programmed data, is reset only when the device is reprogrammed. generic testing each max 7000 device is functionally tested. complete testing of each programmable eeprom bit and all internal logic elements ensures 100 % programming yield. ac test measurements are taken under conditions equivalent to those shown in figure 10 . test patterns can be used and then erased during early stages of the production flow. figure 10. max 7000 ac test conditions qfp carrier & development socket max 7000 and max 7000e devices in qfp packages with 100 or more pins are shipped in special plastic carriers to protect the qfp leads. the carrier is used with a prototype development socket and special programming hardware available from altera. this carrier technology makes it possible to program, test, erase, and reprogram a device without exposing the leads to mechanical stress. f for detailed information and carrier dimensions, refer to the qfp carrier & development socket data sheet . 1 max 7000s devices are not shipped in carriers. vcc to test system c1 (includes jig capacitance) device input rise and fall times < 3 ns device output 464 ? [703 ? ] 250 [8.06 ] ? k ? power supply transients can affect ac measurements. simultaneous transitions of multiple outputs should be avoided for accurate measurement. threshold tests must not be performed under ac conditions. large-amplitude, fast ground-current transients normally occur as the device outputs discharge the load capacitances. when these transients flow through the parasitic inductance between the device ground pin and the test system ground, significant reductions in observable noise immunity can result. numbers in brackets are for 2.5-v devices and outputs. numbers without brackets are for 3.3-v devices and outputs.
altera corporation 23 max 7000 programmable logic device family data sheet operating conditions tables 10 through 15 provide information about absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for 5.0-v max 7000 devices. table 10. max 7000 5.0-v device absolute maximum ratings note (1) symbol parameter conditions min max unit v cc supply voltage with respect to ground (2) ?.0 7.0 v v i dc input voltage 2.0 7.0 v i out dc output current, per pin ?5 25 ma t stg storage temperature no bias ?5 150 c t amb ambient temperature under bias ?5 135 c t j junction temperature ceramic packages, under bias 150 c pqfp and rqfp packages, under bias 135 c table 11. max 7000 5.0-v device recommended operating conditions symbol parameter conditions min max unit v ccint supply voltage for internal logic and input buffers (3) , (4) , (5) 4.75 (4.50) 5.25 (5.50) v v ccio supply voltage for output drivers, 5.0-v operation (3) , (4) 4.75 (4.50) 5.25 (5.50) v supply voltage for output drivers, 3.3-v operation (3) , (4) , (6) 3.00 (3.00) 3.60 (3.60) v v ccisp supply voltage during isp (7) 4.75 5.25 v v i input voltage ?.5 (8) v ccint + 0.5 v v o output voltage 0v ccio v t a ambient temperature for commercial use 0 70 ?c for industrial use ?0 85 ?c t j junction temperature for commercial use 0 90 ?c for industrial use ?0 105 ?c t r input rise time 40 ns t f input fall time 40 ns
24 altera corporation max 7000 programmable logic device family data sheet table 12. max 7000 5.0-v device dc operating conditions note (9) symbol parameter conditions min max unit v ih high-level input voltage 2.0 v ccint + 0.5 v v il low-level input voltage ?.5 (8) 0.8 v v oh 5.0-v high-level ttl output voltage i oh = ? ma dc, v ccio = 4.75 v (10) 2.4 v 3.3-v high-level ttl output voltage i oh = ? ma dc, v ccio = 3.00 v (10) 2.4 v 3.3-v high-level cmos output voltage i oh = ?.1 ma dc, v ccio = 3.0 v (10) v ccio ?0.2 v v ol 5.0-v low-level ttl output voltage i ol = 12 ma dc, v ccio = 4.75 v (11) 0.45 v 3.3-v low-level ttl output voltage i ol = 12 ma dc, v ccio = 3.00 v (11) 0.45 v 3.3-v low-level cmos output voltage i ol = 0.1 ma dc, v ccio = 3.0 v (11) 0.2 v i i leakage current of dedicated input pins v i = ?.5 to 5.5 v (11) ?0 10 a i oz i/o pin tri-state output off-state current v i = ?.5 to 5.5 v (11) , (12) ?0 40 a table 13. max 7000 5.0-v device capacitance: epm7032, epm7064 & epm7096 devices note (13) symbol parameter conditions min max unit c in input pin capacitance v in = 0 v, f = 1.0 mhz 12 pf c i/o i/o pin capacitance v out = 0 v, f = 1.0 mhz 12 pf table 14. max 7000 5.0-v device capacitance: max 7000e devices note (13) symbol parameter conditions min max unit c in input pin capacitance v in = 0 v, f = 1.0 mhz 15 pf c i/o i/o pin capacitance v out = 0 v, f = 1.0 mhz 15 pf table 15. max 7000 5.0-v device capacitance: max 7000s devices note (13) symbol parameter conditions min max unit c in dedicated input pin capacitance v in = 0 v, f = 1.0 mhz 10 pf c i/o i/o pin capacitance v out = 0 v, f = 1.0 mhz 10 pf
altera corporation 25 max 7000 programmable logic device family data sheet notes to tables: (1) see the operating requirements for altera devices data sheet . (2) minimum dc input voltage on i/o pins is ?0.5 v and on 4 dedicated input pins is ?0.3 v. during transitions, the inputs may undershoot to ?2.0 v or overshoot to 7.0 v for input currents less than 100 ma and periods shorter than 20 ns. (3) numbers in parentheses are for industrial-temperature-range devices. (4) v cc must rise monotonically. (5) the por time for all 7000s devices does not exceed 300 s. the sufficient v ccint voltage level for por is 4.5 v. the device is fully initialized within the por time after v ccint reaches the sufficient por voltage level. (6) 3.3-v i/o operation is not available for 44-pin packages. (7) the v ccisp parameter applies only to max 7000s devices. (8) during in-system programming, the minimum dc input voltage is ?0.3 v. (9) these values are specified under the max 7000 recommended operating conditions in table 11 on page 23 . (10) the parameter is measured with 50 % of the outputs each sourcing the specified current. the i oh parameter refers to high-level ttl or cmos output current. (11) the parameter is measured with 50 % of the outputs each sinking the specified current. the i ol parameter refers to low-level ttl, pci, or cmos output current. (12) when the jtag interface is enabled in max 7000s devices, the input leakage current on the jtag pins is typically ?60 a. (13) capacitance is measured at 25 c and is sample-tested only. the oe1 pin has a maximum capacitance of 20 pf. figure 11 shows the typical output drive characteristics of max 7000 devices. figure 11. output drive characteristics of 5.0-v max 7000 devices timing model max 7000 device timing can be analyzed with the altera software, with a variety of popular industry-standard eda simulators and timing analyzers, or with the timing model shown in figure 12 . max 7000 devices have fixed internal delays that enable the designer to determine the worst-case timing of any design. the altera software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for a device-wide performance evaluation. v o output voltage (v) 12345 30 60 90 150 120 v c cio = 3.3 v i ol i oh room temperature 3.3 v o output voltage (v) 12345 30 60 90 150 120 v ccio = 5.0 v i ol i oh room temperature i o t ypical o utput c urrent (ma) i o typical output current (ma)
26 altera corporation max 7000 programmable logic device family data sheet figure 12. max 7000 timing model notes: (1) only available in max 7000e and max 7000s devices. (2) not available in 44-pin devices. the timing characteristics of any signal path can be derived from the timing model and parameters of a particular device. external timing parameters, which represent pin-to-pin timing delays, can be calculated as the sum of internal parameters. figure 13 shows the internal timing relationship of internal and external delay parameters. f for more infomration, see application note 94 (understanding max 7000 timing) . logic array delay t lad output delay t od3 t od2 t od1 t xz z t x1 t zx2 t zx3 input delay t in register delay t su t h t pre t clr t rd t comb t fsu t fh pia delay t pia shared expander delay t sexp register control delay t lac t ic t en i/o delay t io global control delay t glob internal output enable delay t ioe parallel expander delay t pexp fast input delay t fin (1) (2) (1) (1) (2)
altera corporation 27 max 7000 programmable logic device family data sheet figure 13. switching waveforms combinatorial mode input pin i/o pin pia delay shared expander delay logic array input parallel expander delay logic array output output pin t in t lac , t lad t pia t od t pexp t io t sexp t comb global clock mode global clock pin global clock at register data or enable (logic array output) t f t ch t cl t r t in t glob t su t h array clock mode input or i/o pin clock into pia clock into logic array clock at register data from logic array register to pia to logic array register output to pin t f t r t ach t acl t su t in t io t rd t pia t clr , t pre t h t pia t ic t pia t od t od t r & t f < 3 ns. inputs are driven at 3 v for a logic high and 0 v for a logic low. all timing characteristics are measured at 1.5 v.
28 altera corporation max 7000 programmable logic device family data sheet tables 16 through 23 show the max 7000 and max 7000e ac operating conditions. table 16. max 7000 & max 7000e external timing parameters note (1) symbol parameter conditions -6 speed grade -7 speed grade unit min max min max t pd1 input to non-registered output c1 = 35 pf 6.0 7.5 ns t pd2 i/o input to non-registered output c1 = 35 pf 6.0 7.5 ns t su global clock setup time 5.0 6.0 ns t h global clock hold time 0.0 0.0 ns t fsu global clock setup time of fast input (2) 2.5 3.0 ns t fh global clock hold time of fast input (2) 0.5 0.5 ns t co1 global clock to output delay c1 = 35 pf 4.0 4.5 ns t ch global clock high time 2.5 3.0 ns t cl global clock low time 2.5 3.0 ns t asu array clock setup time 2.5 3.0 ns t ah array clock hold time 2.0 2.0 ns t aco1 array clock to output delay c1 = 35 pf 6.5 7.5 ns t ach array clock high time 3.0 3.0 ns t acl array clock low time 3.0 3.0 ns t cppw minimum pulse width for clear and preset (3) 3.0 3.0 ns t odh output data hold time after clock c1 = 35 pf (4) 1.0 1.0 ns t cnt minimum global clock period 6.6 8.0 ns f cnt maximum internal global clock frequency (5) 151.5 125.0 mhz t acnt minimum array clock period 6.6 8.0 ns f acnt maximum internal array clock frequency (5) 151.5 125.0 mhz f max maximum clock frequency (6) 200 166.7 mhz
altera corporation 29 max 7000 programmable logic device family data sheet table 17. max 7000 & max 7000e internal timing parameters note (1) symbol parameter conditions speed grade -6 speed grade -7 unit min max min max t in input pad and buffer delay 0.4 0.5 ns t io i/o input pad and buffer delay 0.4 0.5 ns t fin fast input delay (2) 0.8 1.0 ns t sexp shared expander delay 3.5 4.0 ns t pexp parallel expander delay 0.8 0.8 ns t lad logic array delay 2.0 3.0 ns t lac logic control array delay 2.0 3.0 ns t ioe internal output enable delay (2) 2.0 ns t od1 output buffer and pad delay slow slew rate = off, v ccio = 5.0 v c1 = 35 pf 2.0 2.0 ns t od2 output buffer and pad delay slow slew rate = off, v ccio = 3.3 v c1 = 35 pf (7) 2.5 2.5 ns t od3 output buffer and pad delay slow slew rate = on, v ccio = 5.0 v or 3.3 v c1 = 35 pf (2) 7.0 7.0 ns t zx1 output buffer enable delay slow slew rate = off, v ccio = 5.0 v c1 = 35 pf 4.0 4.0 ns t zx2 output buffer enable delay slow slew rate = off, v ccio = 3.3 v c1 = 35 pf (7) 4.5 4.5 ns t zx3 output buffer enable delay slow slew rate = on v ccio = 5.0 v or 3.3 v c1 = 35 pf (2) 9.0 9.0 ns t xz output buffer disable delay c1 = 5 pf 4.0 4.0 ns t su register setup time 3.0 3.0 ns t h register hold time 1.5 2.0 ns t fsu register setup time of fast input (2) 2.5 3.0 ns t fh register hold time of fast input (2) 0.5 0.5 ns t rd register delay 0.8 1.0 ns t comb combinatorial delay 0.8 1.0 ns t ic array clock delay 2.5 3.0 ns t en register enable time 2.0 3.0 ns t glob global control delay 0.8 1.0 ns t pre register preset time 2.0 2.0 ns t clr register clear time 2.0 2.0 ns t pia pia delay 0.8 1.0 ns t lpa low-power adder (8) 10.0 10.0 ns
30 altera corporation max 7000 programmable logic device family data sheet table 18. max 7000 & max 7000e external timing parameters note (1) symbol parameter conditions speed grade unit max 7000e (-10p) max 7000 (-10) max 7000e (-10) min max min max t pd1 input to non-registered output c1 = 35 pf 10.0 10.0 ns t pd2 i/o input to non-registered output c1 = 35 pf 10.0 10.0 ns t su global clock setup time 7.0 8.0 ns t h global clock hold time 0.0 0.0 ns t fsu global clock setup time of fast input (2) 3.0 3.0 ns t fh global clock hold time of fast input (2) 0.5 0.5 ns t co1 global clock to output delay c1 = 35 pf 5.0 5 ns t ch global clock high time 4.0 4.0 ns t cl global clock low time 4.0 4.0 ns t asu array clock setup time 2.0 3.0 ns t ah array clock hold time 3.0 3.0 ns t aco1 array clock to output delay c1 = 35 pf 10.0 10.0 ns t ach array clock high time 4.0 4.0 ns t acl array clock low time 4.0 4.0 ns t cppw minimum pulse width for clear and preset (3) 4.0 4.0 ns t odh output data hold time after clock c1 = 35 pf (4) 1.0 1.0 ns t cnt minimum global clock period 10.0 10.0 ns f cnt maximum internal global clock frequency (5) 100.0 100.0 mhz t acnt minimum array clock period 10.0 10.0 ns f acnt maximum internal array clock frequency (5) 100.0 100.0 mhz f max maximum clock frequency (6) 125.0 125.0 mhz
altera corporation 31 max 7000 programmable logic device family data sheet table 19. max 7000 & max 7000e internal timing parameters note (1) symbol parameter conditions speed grade unit max 7000e (-10p) max 7000 (-10) max 7000e (-10) min max min max t in input pad and buffer delay 0.5 1.0 ns t io i/o input pad and buffer delay 0.5 1.0 ns t fin fast input delay (2) 1.0 1.0 ns t sexp shared expander delay 5.0 5.0 ns t pexp parallel expander delay 0.8 0.8 ns t lad logic array delay 5.0 5.0 ns t lac logic control array delay 5.0 5.0 ns t ioe internal output enable delay (2) 2.0 2.0 ns t od1 output buffer and pad delay slow slew rate = off v ccio = 5.0 v c1 = 35 pf 1.5 2.0 ns t od2 output buffer and pad delay slow slew rate = off v ccio = 3.3 v c1 = 35 pf (7) 2.0 2.5 ns t od3 output buffer and pad delay slow slew rate = on v ccio = 5.0 v or 3.3 v c1 = 35 pf (2) 5.5 6.0 ns t zx1 output buffer enable delay slow slew rate = off v ccio = 5.0 v c1 = 35 pf 5.0 5.0 ns t zx2 output buffer enable delay slow slew rate = off v ccio = 3.3 v c1 = 35 pf (7) 5.5 5.5 ns t zx3 output buffer enable delay slow slew rate = on v ccio = 5.0 v or 3.3 v c1 = 35 pf (2) 9.0 9.0 ns t xz output buffer disable delay c1 = 5 pf 5.0 5.0 ns t su register setup time 2.0 3.0 ns t h register hold time 3.0 3.0 ns t fsu register setup time of fast input (2) 3.0 3.0 ns t fh register hold time of fast input (2) 0.5 0.5 ns t rd register delay 2.0 1.0 ns t comb combinatorial delay 2.0 1.0 ns t ic array clock delay 5.0 5.0 ns t en register enable time 5.0 5.0 ns t glob global control delay 1.0 1.0 ns t pre register preset time 3.0 3.0 ns t clr register clear time 3.0 3.0 ns t pia pia delay 1.0 1.0 ns t lpa low-power adder (8) 11.0 11.0 ns
32 altera corporation max 7000 programmable logic device family data sheet table 20. max 7000 & max 7000e external timing parameters note (1) symbol parameter conditions speed grade unit max 7000e (-12p) max 7000 (-12) max 7000e (-12) min max min max t pd1 input to non-registered output c1 = 35 pf 12.0 12.0 ns t pd2 i/o input to non-registered output c1 = 35 pf 12.0 12.0 ns t su global clock setup time 7.0 10.0 ns t h global clock hold time 0.0 0.0 ns t fsu global clock setup time of fast input (2) 3.0 3.0 ns t fh global clock hold time of fast input (2) 0.0 0.0 ns t co1 global clock to output delay c1 = 35 pf 6.0 6.0 ns t ch global clock high time 4.0 4.0 ns t cl global clock low time 4.0 4.0 ns t asu array clock setup time 3.0 4.0 ns t ah array clock hold time 4.0 4.0 ns t aco1 array clock to output delay c1 = 35 pf 12.0 12.0 ns t ach array clock high time 5.0 5.0 ns t acl array clock low time 5.0 5.0 ns t cppw minimum pulse width for clear and preset (3) 5.0 5.0 ns t odh output data hold time after clock c1 = 35 pf (4) 1.0 1.0 ns t cnt minimum global clock period 11.0 11.0 ns f cnt maximum internal global clock frequency (5) 90.9 90.9 mhz t acnt minimum array clock period 11.0 11.0 ns f acnt maximum internal array clock frequency (5) 90.9 90.9 mhz f max maximum clock frequency (6) 125.0 125.0 mhz
altera corporation 33 max 7000 programmable logic device family data sheet table 21. max 7000 & max 7000e internal timing parameters note (1) symbol parameter conditions speed grade unit max 7000e (-12p) max 7000 (-12) max 7000e (-12) min max min max t in input pad and buffer delay 1.0 2.0 ns t io i/o input pad and buffer delay 1.0 2.0 ns t fin fast input delay (2) 1.0 1.0 ns t sexp shared expander delay 7.0 7.0 ns t pexp parallel expander delay 1.0 1.0 ns t lad logic array delay 7.0 5.0 ns t lac logic control array delay 5.0 5.0 ns t ioe internal output enable delay (2) 2.0 2.0 ns t od1 output buffer and pad delay slow slew rate = off v ccio = 5.0 v c1 = 35 pf 1.0 3.0 ns t od2 output buffer and pad delay slow slew rate = off v ccio = 3.3 v c1 = 35 pf (7) 2.0 4.0 ns t od3 output buffer and pad delay slow slew rate = on v ccio = 5.0 v or 3.3 v c1 = 35 pf (2) 5.0 7.0 ns t zx1 output buffer enable delay slow slew rate = off v ccio = 5.0 v c1 = 35 pf 6.0 6.0 ns t zx2 output buffer enable delay slow slew rate = off v ccio = 3.3 v c1 = 35 pf (7) 7.0 7.0 ns t zx3 output buffer enable delay slow slew rate = on v ccio = 5.0 v or 3.3 v c1 = 35 pf (2) 10.0 10.0 ns t xz output buffer disable delay c1 = 5 pf 6.0 6.0 ns t su register setup time 1.0 4.0 ns t h register hold time 6.0 4.0 ns t fsu register setup time of fast input (2) 4.0 2.0 ns t fh register hold time of fast input (2) 0.0 2.0 ns t rd register delay 2.0 1.0 ns t comb combinatorial delay 2.0 1.0 ns t ic array clock delay 5.0 5.0 ns t en register enable time 7.0 5.0 ns t glob global control delay 2.0 0.0 ns t pre register preset time 4.0 3.0 ns t clr register clear time 4.0 3.0 ns t pia pia delay 1.0 1.0 ns t lpa low-power adder (8) 12.0 12.0 ns
34 altera corporation max 7000 programmable logic device family data sheet table 22. max 7000 & max 7000e external timing parameters note (1) symbol parameter conditions speed grade unit -15 -15t -20 min max min max min max t pd1 input to non-registered output c1 = 35 pf 15.0 15.0 20.0 ns t pd2 i/o input to non-registered output c1 = 35 pf 15.0 15.0 20.0 ns t su global clock setup time 11.0 11.0 12.0 ns t h global clock hold time 0.0 0.0 0.0 ns t fsu global clock setup time of fast input (2) 3.0 5.0 ns t fh global clock hold time of fast input (2) 0.0 0.0 ns t co1 global clock to output delay c1 = 35 pf 8.0 8.0 12.0 ns t ch global clock high time 5.0 6.0 6.0 ns t cl global clock low time 5.0 6.0 6.0 ns t asu array clock setup time 4.0 4.0 5.0 ns t ah array clock hold time 4.0 4.0 5.0 ns t aco1 array clock to output delay c1 = 35 pf 15.0 15.0 20.0 ns t ach array clock high time 6.0 6.5 8.0 ns t acl array clock low time 6.0 6.5 8.0 ns t cppw minimum pulse width for clear and preset (3) 6.0 6.5 8.0 ns t odh output data hold time after clock c1 = 35 pf (4) 1.0 1.0 1.0 ns t cnt minimum global clock period 13.0 13.0 16.0 ns f cnt maximum internal global clock frequency (5) 76.9 76.9 62.5 mhz t acnt minimum array clock period 13.0 13.0 16.0 ns f acnt maximum internal array clock frequency (5) 76.9 76.9 62.5 mhz f max maximum clock frequency (6) 100 83.3 83.3 mhz
altera corporation 35 max 7000 programmable logic device family data sheet table 23. max 7000 & max 7000e internal timing parameters note (1) symbol parameter conditions speed grade unit -15 -15t -20 min max min max min max t in input pad and buffer delay 2.0 2.0 3.0 ns t io i/o input pad and buffer delay 2.0 2.0 3.0 ns t fin fast input delay (2) 2.0 4.0 ns t sexp shared expander delay 8.0 10.0 9.0 ns t pexp parallel expander delay 1.0 1.0 2.0 ns t lad logic array delay 6.0 6.0 8.0 ns t lac logic control array delay 6.0 6.0 8.0 ns t ioe internal output enable delay (2) 3.0 4.0 ns t od1 output buffer and pad delay slow slew rate = off v ccio = 5.0 v c1 = 35 pf 4.0 4.0 5.0 ns t od2 output buffer and pad delay slow slew rate = off v ccio = 3.3 v c1 = 35 pf (7) 5.0 6.0 ns t od3 output buffer and pad delay slow slew rate = on v ccio = 5.0 v or 3.3 v c1 = 35 pf (2) 8.0 9.0 ns t zx1 output buffer enable delay slow slew rate = off v ccio = 5.0 v c1 = 35 pf 6.0 6.0 10.0 ns t zx2 output buffer enable delay slow slew rate = off v ccio = 3.3 v c1 = 35 pf (7) 7.0 11.0 ns t zx3 output buffer enable delay slow slew rate = on v ccio = 5.0 v or 3.3 v c1 = 35 pf (2) 10.0 14.0 ns t xz output buffer disable delay c1 = 5 pf 6.0 6.0 10.0 ns t su register setup time 4.0 4.0 4.0 ns t h register hold time 4.0 4.0 5.0 ns t fsu register setup time of fast input (2) 2.0 4.0 ns t fh register hold time of fast input (2) 2.0 3.0 ns t rd register delay 1.0 1.0 1.0 ns t comb combinatorial delay 1.0 1.0 1.0 ns t ic array clock delay 6.0 6.0 8.0 ns t en register enable time 6.0 6.0 8.0 ns t glob global control delay 1.0 1.0 3.0 ns t pre register preset time 4.0 4.0 4.0 ns t clr register clear time 4.0 4.0 4.0 ns t pia pia delay 2.0 2.0 3.0 ns t lpa low-power adder (8) 13.0 15.0 15.0 ns
36 altera corporation max 7000 programmable logic device family data sheet notes to tables: (1) these values are specified under the recommended operating conditions shown in table 11 . see figure 13 for more information on switching waveforms. (2) this parameter applies to max 7000e devices only. (3) this minimum pulse width for preset and clear applies for both global clear and array controls. the t lpa parameter must be added to this minimum width if the clear or reset signal incorporates the t lad parameter into the signal path. (4) this parameter is a guideline that is sample-tested only and is based on extensive device characterization. this parameter applies for both global and array clocking. (5) these parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each lab. (6) the f max values represent the highest frequency for pipelined data. (7) operating conditions: v ccio = 3.3 v 10 % for commercial and industrial use. (8) the t lpa parameter must be added to the t lad , t lac , t ic , t en , t sexp , t acl , and t cppw parameters for macrocells running in the low-power mode. tables 24 and 25 show the epm7032s ac operating conditions. table 24. epm7032s external timing parameters (part 1 of 2) note (1) symbol parameter conditions speed grade unit -5 -6 -7 -10 min max min max min max min max t pd1 input to non-registered output c1 = 35 pf 5.0 6.0 7.5 10.0 ns t pd2 i/o input to non-registered output c1 = 35 pf 5.0 6.0 7.5 10.0 ns t su global clock setup time 2.9 4.0 5.0 7.0 ns t h global clock hold time 0.0 0.0 0.0 0.0 ns t fsu global clock setup time of fast input 2.5 2.5 2.5 3.0 ns t fh global clock hold time of fast input 0.0 0.0 0.0 0.5 ns t co1 global clock to output delay c1 = 35 pf 3.2 3.5 4.3 5.0 ns t ch global clock high time 2.0 2.5 3.0 4.0 ns t cl global clock low time 2.0 2.5 3.0 4.0 ns t asu array clock setup time 0.7 0.9 1.1 2.0 ns t ah array clock hold time 1.8 2.1 2.7 3.0 ns t aco1 array clock to output delay c1 = 35 pf 5.4 6.6 8.2 10.0 ns t ach array clock high time 2.5 2.5 3.0 4.0 ns t acl array clock low time 2.5 2.5 3.0 4.0 ns t cppw minimum pulse width for clear and preset (2) 2.5 2.5 3.0 4.0 ns t odh output data hold time after clock c1 = 35 pf (3) 1.0 1.0 1.0 1.0 ns t cnt minimum global clock period 5.7 7.0 8.6 10.0 ns f cnt maximum internal global clock frequency (4) 175.4 142.9 116.3 100.0 mhz t acnt minimum array clock period 5.7 7.0 8.6 10.0 ns
altera corporation 37 max 7000 programmable logic device family data sheet f acnt maximum internal array clock frequency (4) 175.4 142.9 116.3 100.0 mhz f max maximum clock frequency (5) 250.0 200.0 166.7 125.0 mhz table 25. epm7032s internal timing parameters note (1) symbol parameter conditions speed grade unit -5 -6 -7 -10 minmaxminmaxminmaxminmax t in input pad and buffer delay 0.2 0.2 0.3 0.5 ns t io i/o input pad and buffer delay 0.2 0.2 0.3 0.5 ns t fin fast input delay 2.2 2.1 2.5 1.0 ns t sexp shared expander delay 3.1 3.8 4.6 5.0 ns t pexp parallel expander delay 0.9 1.1 1.4 0.8 ns t lad logic array delay 2.6 3.3 4.0 5.0 ns t lac logic control array delay 2.5 3.3 4.0 5.0 ns t ioe internal output enable delay 0.7 0.8 1.0 2.0 ns t od1 output buffer and pad delay c1 = 35 pf 0.2 0.3 0.4 1.5 ns t od2 output buffer and pad delay c1 = 35 pf (6) 0.7 0.8 0.9 2.0 ns t od3 output buffer and pad delay c1 = 35 pf 5.2 5.3 5.4 5.5 ns t zx1 output buffer enable delay c1 = 35 pf 4.0 4.0 4.0 5.0 ns t zx2 output buffer enable delay c1 = 35 pf (6) 4.5 4.5 4.5 5.5 ns t zx3 output buffer enable delay c1 = 35 pf 9.0 9.0 9.0 9.0 ns t xz output buffer disable delay c1 = 5 pf 4.0 4.0 4.0 5.0 ns t su register setup time 0.8 1.0 1.3 2.0 ns t h register hold time 1.7 2.0 2.5 3.0 ns t fsu register setup time of fast input 1.9 1.8 1.7 3.0 ns t fh register hold time of fast input 0.6 0.7 0.8 0.5 ns t rd register delay 1.2 1.6 1.9 2.0 ns t comb combinatorial delay 0.9 1.1 1.4 2.0 ns t ic array clock delay 2.7 3.4 4.2 5.0 ns t en register enable time 2.6 3.3 4.0 5.0 ns t glob global control delay 1.6 1.4 1.7 1.0 ns t pre register preset time 2.0 2.4 3.0 3.0 ns table 24. epm7032s external timing parameters (part 2 of 2) note (1) symbol parameter conditions speed grade unit -5 -6 -7 -10 min max min max min max min max
38 altera corporation max 7000 programmable logic device family data sheet notes to tables: (1) these values are specified under the recommended operating conditions shown in table 11 . see figure 13 for more information on switching waveforms. (2) this minimum pulse width for preset and clear applies for both global clear and array controls. the t lpa parameter must be added to this minimum width if the clear or reset signal incorporates the t lad parameter into the signal path. (3) this parameter is a guideline that is sample-tested only and is based on extensive device characterization. this parameter applies for both global and array clocking. (4) these parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each lab. (5) the f max values represent the highest frequency for pipelined data. (6) operating conditions: v ccio = 3.3 v 10 % for commercial and industrial use. (7) for epm7064s-5, epm7064s-6, epm7128s-6, epm7160s-6, epm7160s-7, epm7192s-7, and epm7256s-7 devices, these values are specified for a pia fan-out of one lab (16 macrocells). for each additional lab fan-out in these devices, add an additional 0.1 ns to the pia timing value. (8) the t lpa parameter must be added to the t lad , t lac , t ic , t en , t sexp , t acl , and t cppw parameters for macrocells running in the low-power mode. tables 26 and 27 show the epm7064s ac operating conditions. t clr register clear time 2.0 2.4 3.0 3.0 ns t pia pia delay (7) 1.1 1.1 1.4 1.0 ns t lpa low-power adder (8) 12.0 10.0 10.0 11.0 ns table 25. epm7032s internal timing parameters note (1) symbol parameter conditions speed grade unit -5 -6 -7 -10 min max min max min max min max table 26. epm7064s external timing parameters (part 1 of 2) note (1) symbol parameter conditions speed grade unit -5 -6 -7 -10 min max min max min max min max t pd1 input to non-registered output c1 = 35 pf 5.0 6.0 7.5 10.0 ns t pd2 i/o input to non-registered output c1 = 35 pf 5.0 6.0 7.5 10.0 ns t su global clock setup time 2.9 3.6 6.0 7.0 ns t h global clock hold time 0.0 0.0 0.0 0.0 ns t fsu global clock setup time of fast input 2.5 2.5 3.0 3.0 ns t fh global clock hold time of fast input 0.0 0.0 0.5 0.5 ns t co1 global clock to output delay c1 = 35 pf 3.2 4.0 4.5 5.0 ns t ch global clock high time 2.0 2.5 3.0 4.0 ns t cl global clock low time 2.0 2.5 3.0 4.0 ns t asu array clock setup time 0.7 0.9 3.0 2.0 ns
altera corporation 39 max 7000 programmable logic device family data sheet t ah array clock hold time 1.8 2.1 2.0 3.0 ns t aco1 array clock to output delay c1 = 35 pf 5.4 6.7 7.5 10.0 ns t ach array clock high time 2.5 2.5 3.0 4.0 ns t acl array clock low time 2.5 2.5 3.0 4.0 ns t cppw minimum pulse width for clear and preset (2) 2.5 2.5 3.0 4.0 ns t odh output data hold time after clock c1 = 35 pf (3) 1.0 1.0 1.0 1.0 ns t cnt minimum global clock period 5.7 7.1 8.0 10.0 ns f cnt maximum internal global clock frequency (4) 175.4 140.8 125.0 100.0 mhz t acnt minimum array clock period 5.7 7.1 8.0 10.0 ns f acnt maximum internal array clock frequency (4) 175.4 140.8 125.0 100.0 mhz f max maximum clock frequency (5) 250.0 200.0 166.7 125.0 mhz table 27. epm7064s internal timing parameters (part 1 of 2) note (1) symbol parameter conditions speed grade unit -5 -6 -7 -10 min max min max min max min max t in input pad and buffer delay 0.2 0.2 0.5 0.5 ns t io i/o input pad and buffer delay 0.2 0.2 0.5 0.5 ns t fin fast input delay 2.2 2.6 1.0 1.0 ns t sexp shared expander delay 3.1 3.8 4.0 5.0 ns t pexp parallel expander delay 0.9 1.1 0.8 0.8 ns t lad logic array delay 2.6 3.2 3.0 5.0 ns t lac logic control array delay 2.5 3.2 3.0 5.0 ns t ioe internal output enable delay 0.7 0.8 2.0 2.0 ns t od1 output buffer and pad delay c1 = 35 pf 0.2 0.3 2.0 1.5 ns t od2 output buffer and pad delay c1 = 35 pf (6) 0.7 0.8 2.5 2.0 ns t od3 output buffer and pad delay c1 = 35 pf 5.2 5.3 7.0 5.5 ns t zx1 output buffer enable delay c1 = 35 pf 4.0 4.0 4.0 5.0 ns t zx2 output buffer enable delay c1 = 35 pf (6) 4.5 4.5 4.5 5.5 ns t zx3 output buffer enable delay c1 = 35 pf 9.0 9.0 9.0 9.0 ns t xz output buffer disable delay c1 = 5 pf 4.0 4.0 4.0 5.0 ns t su register setup time 0.8 1.0 3.0 2.0 ns table 26. epm7064s external timing parameters (part 2 of 2) note (1) symbol parameter conditions speed grade unit -5 -6 -7 -10 minmaxminmaxminmaxminmax
40 altera corporation max 7000 programmable logic device family data sheet notes to tables: (1) these values are specified under the recommended operating conditions shown in table 11 . see figure 13 for more information on switching waveforms. (2) this minimum pulse width for preset and clear applies for both global clear and array controls. the t lpa parameter must be added to this minimum width if the clear or reset signal incorporates the t lad parameter into the signal path. (3) this parameter is a guideline that is sample-tested only and is based on extensive device characterization. this parameter applies for both global and array clocking. (4) these parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each lab. (5) the f max values represent the highest frequency for pipelined data. (6) operating conditions: v ccio = 3.3 v 10 % for commercial and industrial use. (7) for epm7064s-5, epm7064s-6, epm7128s-6, epm7160s-6, epm7160s-7, epm7192s-7, and epm7256s-7 devices, these values are specified for a pia fan-out of one lab (16 macrocells). for each additional lab fan-out in these devices, add an additional 0.1 ns to the pia timing value. (8) the t lpa parameter must be added to the t lad , t lac , t ic , t en , t sexp , t acl , and t cppw parameters for macrocells running in the low-power mode. t h register hold time 1.7 2.0 2.0 3.0 ns t fsu register setup time of fast input 1.9 1.8 3.0 3.0 ns t fh register hold time of fast input 0.6 0.7 0.5 0.5 ns t rd register delay 1.2 1.6 1.0 2.0 ns t comb combinatorial delay 0.9 1.0 1.0 2.0 ns t ic array clock delay 2.7 3.3 3.0 5.0 ns t en register enable time 2.6 3.2 3.0 5.0 ns t glob global control delay 1.6 1.9 1.0 1.0 ns t pre register preset time 2.0 2.4 2.0 3.0 ns t clr register clear time 2.0 2.4 2.0 3.0 ns t pia pia delay (7) 1.1 1.3 1.0 1.0 ns t lpa low-power adder (8) 12.0 11.0 10.0 11.0 ns table 27. epm7064s internal timing parameters (part 2 of 2) note (1) symbol parameter conditions speed grade unit -5 -6 -7 -10 min max min max min max min max
altera corporation 41 max 7000 programmable logic device family data sheet tables 28 and 29 show the epm7128s ac operating conditions. table 28. epm7128s external timing parameters note (1) symbol parameter conditions speed grade unit -6 -7 -10 -15 minmaxminmaxminmaxminmax t pd1 input to non-registered output c1 = 35 pf 6.0 7.5 10.0 15.0 ns t pd2 i/o input to non-registered output c1 = 35 pf 6.0 7.5 10.0 15.0 ns t su global clock setup time 3.4 6.0 7.0 11.0 ns t h global clock hold time 0.0 0.0 0.0 0.0 ns t fsu global clock setup time of fast input 2.5 3.0 3.0 3.0 ns t fh global clock hold time of fast input 0.0 0.5 0.5 0.0 ns t co1 global clock to output delay c1 = 35 pf 4.0 4.5 5.0 8.0 ns t ch global clock high time 3.0 3.0 4.0 5.0 ns t cl global clock low time 3.0 3.0 4.0 5.0 ns t asu array clock setup time 0.9 3.0 2.0 4.0 ns t ah array clock hold time 1.8 2.0 5.0 4.0 ns t aco1 array clock to output delay c1 = 35 pf 6.5 7.5 10.0 15.0 ns t ach array clock high time 3.0 3.0 4.0 6.0 ns t acl array clock low time 3.0 3.0 4.0 6.0 ns t cppw minimum pulse width for clear and preset (2) 3.0 3.0 4.0 6.0 ns t odh output data hold time after clock c1 = 35 pf (3) 1.0 1.0 1.0 1.0 ns t cnt minimum global clock period 6.8 8.0 10.0 13.0 ns f cnt maximum internal global clock frequency (4) 147.1 125.0 100.0 76.9 mhz t acnt minimum array clock period 6.8 8.0 10.0 13.0 ns f acnt maximum internal array clock frequency (4) 147.1 125.0 100.0 76.9 mhz f max maximum clock frequency (5) 166.7 166.7 125.0 100.0 mhz
42 altera corporation max 7000 programmable logic device family data sheet table 29. epm7128s internal timing parameters note (1) symbol parameter conditions speed grade unit -6 -7 -10 -15 min max min max min max min max t in input pad and buffer delay 0.2 0.5 0.5 2.0 ns t io i/o input pad and buffer delay 0.2 0.5 0.5 2.0 ns t fin fast input delay 2.6 1.0 1.0 2.0 ns t sexp shared expander delay 3.7 4.0 5.0 8.0 ns t pexp parallel expander delay 1.1 0.8 0.8 1.0 ns t lad logic array delay 3.0 3.0 5.0 6.0 ns t lac logic control array delay 3.0 3.0 5.0 6.0 ns t ioe internal output enable delay 0.7 2.0 2.0 3.0 ns t od1 output buffer and pad delay c1 = 35 pf 0.4 2.0 1.5 4.0 ns t od2 output buffer and pad delay c1 = 35 pf (6) 0.9 2.5 2.0 5.0 ns t od3 output buffer and pad delay c1 = 35 pf 5.4 7.0 5.5 8.0 ns t zx1 output buffer enable delay c1 = 35 pf 4.0 4.0 5.0 6.0 ns t zx2 output buffer enable delay c1 = 35 pf (6) 4.5 4.5 5.5 7.0 ns t zx3 output buffer enable delay c1 = 35 pf 9.0 9.0 9.0 10.0 ns t xz output buffer disable delay c1 = 5 pf 4.0 4.0 5.0 6.0 ns t su register setup time 1.0 3.0 2.0 4.0 ns t h register hold time 1.7 2.0 5.0 4.0 ns t fsu register setup time of fast input 1.9 3.0 3.0 2.0 ns t fh register hold time of fast input 0.6 0.5 0.5 1.0 ns t rd register delay 1.4 1.0 2.0 1.0 ns t comb combinatorial delay 1.0 1.0 2.0 1.0 ns t ic array clock delay 3.1 3.0 5.0 6.0 ns t en register enable time 3.0 3.0 5.0 6.0 ns t glob global control delay 2.0 1.0 1.0 1.0 ns t pre register preset time 2.4 2.0 3.0 4.0 ns t clr register clear time 2.4 2.0 3.0 4.0 ns t pia pia delay (7) 1.4 1.0 1.0 2.0 ns t lpa low-power adder (8) 11.0 10.0 11.0 13.0 ns
altera corporation 43 max 7000 programmable logic device family data sheet notes to tables: (1) these values are specified under the recommended operating conditions shown in table 11 . see figure 13 for more information on switching waveforms. (2) this minimum pulse width for preset and clear applies for both global clear and array controls. the t lpa parameter must be added to this minimum width if the clear or reset signal incorporates the t lad parameter into the signal path. (3) this parameter is a guideline that is sample-tested only and is based on extensive device characterization. this parameter applies for both global and array clocking. (4) these parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each lab. (5) the f max values represent the highest frequency for pipelined data. (6) operating conditions: v ccio = 3.3 v 10 % for commercial and industrial use. (7) for epm7064s-5, epm7064s-6, epm7128s-6, epm7160s-6, epm7160s-7, epm7192s-7, and epm7256s-7 devices, these values are specified for a pia fan-out of one lab (16 macrocells). for each additional lab fan-out in these devices, add an additional 0.1 ns to the pia timing value. (8) the t lpa parameter must be added to the t lad , t lac , t ic , t en , t sexp , t acl , and t cppw parameters for macrocells running in the low-power mode. tables 30 and 31 show the epm7160s ac operating conditions. table 30. epm7160s external timing parameters (part 1 of 2) note (1) symbol parameter conditions speed grade unit -6 -7 -10 -15 min max min max min max min max t pd1 input to non-registered output c1 = 35 pf 6.0 7.5 10.0 15.0 ns t pd2 i/o input to non-registered output c1 = 35 pf 6.0 7.5 10.0 15.0 ns t su global clock setup time 3.4 4.2 7.0 11.0 ns t h global clock hold time 0.0 0.0 0.0 0.0 ns t fsu global clock setup time of fast input 2.5 3.0 3.0 3.0 ns t fh global clock hold time of fast input 0.0 0.0 0.5 0.0 ns t co1 global clock to output delay c1 = 35 pf 3.9 4.8 5 8 ns t ch global clock high time 3.0 3.0 4.0 5.0 ns t cl global clock low time 3.0 3.0 4.0 5.0 ns t asu array clock setup time 0.9 1.1 2.0 4.0 ns t ah array clock hold time 1.7 2.1 3.0 4.0 ns t aco1 array clock to output delay c1 = 35 pf 6.4 7.9 10.0 15.0 ns t ach array clock high time 3.0 3.0 4.0 6.0 ns t acl array clock low time 3.0 3.0 4.0 6.0 ns t cppw minimum pulse width for clear and preset (2) 2.5 3.0 4.0 6.0 ns t odh output data hold time after clock c1 = 35 pf (3) 1.0 1.0 1.0 1.0 ns t cnt minimum global clock period 6.7 8.2 10.0 13.0 ns f cnt maximum internal global clock frequency (4) 149.3 122.0 100.0 76.9 mhz
44 altera corporation max 7000 programmable logic device family data sheet t acnt minimum array clock period 6.7 8.2 10.0 13.0 ns f acnt maximum internal array clock frequency (4) 149.3 122.0 100.0 76.9 mhz f max maximum clock frequency (5) 166.7 166.7 125.0 100.0 mhz table 31. epm7160s internal timing parameters (part 1 of 2) note (1) symbol parameter conditions speed grade unit -6 -7 -10 -15 min max min max min max min max t in input pad and buffer delay 0.2 0.3 0.5 2.0 ns t io i/o input pad and buffer delay 0.2 0.3 0.5 2.0 ns t fin fast input delay 2.6 3.2 1.0 2.0 ns t sexp shared expander delay 3.6 4.3 5.0 8.0 ns t pexp parallel expander delay 1.0 1.3 0.8 1.0 ns t lad logic array delay 2.8 3.4 5.0 6.0 ns t lac logic control array delay 2.8 3.4 5.0 6.0 ns t ioe internal output enable delay 0.7 0.9 2.0 3.0 ns t od1 output buffer and pad delay c1 = 35 pf 0.4 0.5 1.5 4.0 ns t od2 output buffer and pad delay c1 = 35 pf (6) 0.9 1.0 2.0 5.0 ns t od3 output buffer and pad delay c1 = 35 pf 5.4 5.5 5.5 8.0 ns t zx1 output buffer enable delay c1 = 35 pf 4.0 4.0 5.0 6.0 ns t zx2 output buffer enable delay c1 = 35 pf (6) 4.5 4.5 5.5 7.0 ns t zx3 output buffer enable delay c1 = 35 pf 9.0 9.0 9.0 10.0 ns t xz output buffer disable delay c1 = 5 pf 4.0 4.0 5.0 6.0 ns t su register setup time 1.0 1.2 2.0 4.0 ns t h register hold time 1.6 2.0 3.0 4.0 ns t fsu register setup time of fast input 1.9 2.2 3.0 2.0 ns t fh register hold time of fast input 0.6 0.8 0.5 1.0 ns t rd register delay 1.3 1.6 2.0 1.0 ns t comb combinatorial delay 1.0 1.3 2.0 1.0 ns t ic array clock delay 2.9 3.5 5.0 6.0 ns t en register enable time 2.8 3.4 5.0 6.0 ns t glob global control delay 2.0 2.4 1.0 1.0 ns table 30. epm7160s external timing parameters (part 2 of 2) note (1) symbol parameter conditions speed grade unit -6 -7 -10 -15 minmaxminmaxminmaxminmax
altera corporation 45 max 7000 programmable logic device family data sheet notes to tables: (1) these values are specified under the recommended operating conditions shown in table 11 . see figure 13 for more information on switching waveforms. (2) this minimum pulse width for preset and clear applies for both global clear and array controls. the t lpa parameter must be added to this minimum width if the clear or reset signal incorporates the t lad parameter into the signal path. (3) this parameter is a guideline that is sample-tested only and is based on extensive device characterization. this parameter applies for both global and array clocking. (4) these parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each lab. (5) the f max values represent the highest frequency for pipelined data. (6) operating conditions: v ccio = 3.3 v 10 % for commercial and industrial use. (7) for epm7064s-5, epm7064s-6, epm7128s-6, epm7160s-6, epm7160s-7, epm7192s-7, and epm7256s-7 devices, these values are specified for a pia fan-out of one lab (16 macrocells). for each additional lab fan-out in these devices, add an additional 0.1 ns to the pia timing value. (8) the t lpa parameter must be added to the t lad , t lac , t ic , t en , t sexp , t acl , and t cppw parameters for macrocells running in the low-power mode. tables 32 and 33 show the epm7192s ac operating conditions. t pre register preset time 2.4 3.0 3.0 4.0 ns t clr register clear time 2.4 3.0 3.0 4.0 ns t pia pia delay (7) 1.6 2.0 1.0 2.0 ns t lpa low-power adder (8) 11.0 10.0 11.0 13.0 ns table 31. epm7160s internal timing parameters (part 2 of 2) note (1) symbol parameter conditions speed grade unit -6 -7 -10 -15 min max min max min max min max table 32. epm7192s external timing parameters (part 1 of 2) note (1) symbol parameter conditions speed grade unit -7 -10 -15 minmaxminmaxminmax t pd1 input to non-registered output c1 = 35 pf 7.5 10.0 15.0 ns t pd2 i/o input to non-registered output c1 = 35 pf 7.5 10.0 15.0 ns t su global clock setup time 4.1 7.0 11.0 ns t h global clock hold time 0.0 0.0 0.0 ns t fsu global clock setup time of fast input 3.0 3.0 3.0 ns t fh global clock hold time of fast input 0.0 0.5 0.0 ns t co1 global clock to output delay c1 = 35 pf 4.7 5.0 8.0 ns t ch global clock high time 3.0 4.0 5.0 ns
46 altera corporation max 7000 programmable logic device family data sheet t cl global clock low time 3.0 4.0 5.0 ns t asu array clock setup time 1.0 2.0 4.0 ns t ah array clock hold time 1.8 3.0 4.0 ns t aco1 array clock to output delay c1 = 35 pf 7.8 10.0 15.0 ns t ach array clock high time 3.0 4.0 6.0 ns t acl array clock low time 3.0 4.0 6.0 ns t cppw minimum pulse width for clear and preset (2) 3.0 4.0 6.0 ns t odh output data hold time after clock c1 = 35 pf (3) 1.0 1.0 1.0 ns t cnt minimum global clock period 8.0 10.0 13.0 ns f cnt maximum internal global clock frequency (4) 125.0 100.0 76.9 mhz t acnt minimum array clock period 8.0 10.0 13.0 ns f acnt maximum internal array clock frequency (4) 125.0 100.0 76.9 mhz f max maximum clock frequency (5) 166.7 125.0 100.0 mhz table 33. epm7192s internal timing parameters (part 1 of 2) note (1) symbol parameter conditions speed grade unit -7 -10 -15 min max min max min max t in input pad and buffer delay 0.3 0.5 2.0 ns t io i/o input pad and buffer delay 0.3 0.5 2.0 ns t fin fast input delay 3.2 1.0 2.0 ns t sexp shared expander delay 4.2 5.0 8.0 ns t pexp parallel expander delay 1.2 0.8 1.0 ns t lad logic array delay 3.1 5.0 6.0 ns t lac logic control array delay 3.1 5.0 6.0 ns t ioe internal output enable delay 0.9 2.0 3.0 ns t od1 output buffer and pad delay c1 = 35 pf 0.5 1.5 4.0 ns t od2 output buffer and pad delay c1 = 35 pf (6) 1.0 2.0 5.0 ns t od3 output buffer and pad delay c1 = 35 pf 5.5 5.5 7.0 ns t zx1 output buffer enable delay c1 = 35 pf 4.0 5.0 6.0 ns t zx2 output buffer enable delay c1 = 35 pf (6) 4.5 5.5 7.0 ns t zx3 output buffer enable delay c1 = 35 pf 9.0 9.0 10.0 ns table 32. epm7192s external timing parameters (part 2 of 2) note (1) symbol parameter conditions speed grade unit -7 -10 -15 min max min max min max
altera corporation 47 max 7000 programmable logic device family data sheet notes to tables: (1) these values are specified under the recommended operating conditions shown in table 11 . see figure 13 for more information on switching waveforms. (2) this minimum pulse width for preset and clear applies for both global clear and array controls. the t lpa parameter must be added to this minimum width if the clear or reset signal incorporates the t lad parameter into the signal path. (3) this parameter is a guideline that is sample-tested only and is based on extensive device characterization. this parameter applies for both global and array clocking. (4) these parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each lab. (5) the f max values represent the highest frequency for pipelined data. (6) operating conditions: v ccio = 3.3 v 10 % for commercial and industrial use. (7) for epm7064s-5, epm7064s-6, epm7128s-6, epm7160s-6, epm7160s-7, epm7192s-7, and epm7256s-7 devices, these values are specified for a pia fan-out of one lab (16 macrocells). for each additional lab fan-out in these devices, add an additional 0.1 ns to the pia timing value. (8) the t lpa parameter must be added to the t lad , t lac , t ic , t en , t sexp , t acl , and t cppw parameters for macrocells running in the low-power mode. t xz output buffer disable delay c1 = 5 pf 4.0 5.0 6.0 ns t su register setup time 1.1 2.0 4.0 ns t h register hold time 1.7 3.0 4.0 ns t fsu register setup time of fast input 2.3 3.0 2.0 ns t fh register hold time of fast input 0.7 0.5 1.0 ns t rd register delay 1.4 2.0 1.0 ns t comb combinatorial delay 1.2 2.0 1.0 ns t ic array clock delay 3.2 5.0 6.0 ns t en register enable time 3.1 5.0 6.0 ns t glob global control delay 2.5 1.0 1.0 ns t pre register preset time 2.7 3.0 4.0 ns t clr register clear time 2.7 3.0 4.0 ns t pia pia delay (7) 2.4 1.0 2.0 ns t lpa low-power adder (8) 10.011.013.0ns table 33. epm7192s internal timing parameters (part 2 of 2) note (1) symbol parameter conditions speed grade unit -7 -10 -15 min max min max min max
48 altera corporation max 7000 programmable logic device family data sheet tables 34 and 35 show the epm7256s ac operating conditions. table 34. epm7256s external timing parameters note (1) symbol parameter conditions speed grade unit -7 -10 -15 min max min max min max t pd1 input to non-registered output c1 = 35 pf 7.5 10.0 15.0 ns t pd2 i/o input to non-registered output c1 = 35 pf 7.5 10.0 15.0 ns t su global clock setup time 3.9 7.0 11.0 ns t h global clock hold time 0.0 0.0 0.0 ns t fsu global clock setup time of fast input 3.0 3.0 3.0 ns t fh global clock hold time of fast input 0.0 0.5 0.0 ns t co1 global clock to output delay c1 = 35 pf 4.7 5.0 8.0 ns t ch global clock high time 3.0 4.0 5.0 ns t cl global clock low time 3.0 4.0 5.0 ns t asu array clock setup time 0.8 2.0 4.0 ns t ah array clock hold time 1.9 3.0 4.0 ns t aco1 array clock to output delay c1 = 35 pf 7.8 10.0 15.0 ns t ach array clock high time 3.0 4.0 6.0 ns t acl array clock low time 3.0 4.0 6.0 ns t cppw minimum pulse width for clear and preset (2) 3.0 4.0 6.0 ns t odh output data hold time after clock c1 = 35 pf (3) 1.0 1.0 1.0 ns t cnt minimum global clock period 7.8 10.0 13.0 ns f cnt maximum internal global clock frequency (4) 128.2 100.0 76.9 mhz t acnt minimum array clock period 7.8 10.0 13.0 ns f acnt maximum internal array clock frequency (4) 128.2 100.0 76.9 mhz f max maximum clock frequency (5) 166.7 125.0 100.0 mhz
altera corporation 49 max 7000 programmable logic device family data sheet table 35. epm7256s internal timing parameters note (1) symbol parameter conditions speed grade unit -7 -10 -15 min max min max min max t in input pad and buffer delay 0.3 0.5 2.0 ns t io i/o input pad and buffer delay 0.3 0.5 2.0 ns t fin fast input delay 3.4 1.0 2.0 ns t sexp shared expander delay 3.9 5.0 8.0 ns t pexp parallel expander delay 1.1 0.8 1.0 ns t lad logic array delay 2.6 5.0 6.0 ns t lac logic control array delay 2.6 5.0 6.0 ns t ioe internal output enable delay 0.8 2.0 3.0 ns t od1 output buffer and pad delay c1 = 35 pf 0.5 1.5 4.0 ns t od2 output buffer and pad delay c1 = 35 pf (6) 1.0 2.0 5.0 ns t od3 output buffer and pad delay c1 = 35 pf 5.5 5.5 8.0 ns t zx1 output buffer enable delay c1 = 35 pf 4.0 5.0 6.0 ns t zx2 output buffer enable delay c1 = 35 pf (6) 4.5 5.5 7.0 ns t zx3 output buffer enable delay c1 = 35 pf 9.0 9.0 10.0 ns t xz output buffer disable delay c1 = 5 pf 4.0 5.0 6.0 ns t su register setup time 1.1 2.0 4.0 ns t h register hold time 1.6 3.0 4.0 ns t fsu register setup time of fast input 2.4 3.0 2.0 ns t fh register hold time of fast input 0.6 0.5 1.0 ns t rd register delay 1.1 2.0 1.0 ns t comb combinatorial delay 1.1 2.0 1.0 ns t ic array clock delay 2.9 5.0 6.0 ns t en register enable time 2.6 5.0 6.0 ns t glob global control delay 2.8 1.0 1.0 ns t pre register preset time 2.7 3.0 4.0 ns t clr register clear time 2.7 3.0 4.0 ns t pia pia delay (7) 3.0 1.0 2.0 ns t lpa low-power adder (8) 10.011.013.0ns
50 altera corporation max 7000 programmable logic device family data sheet notes to tables: (1) these values are specified under the recommended operating conditions shown in table 11 . see figure 13 for more information on switching waveforms. (2) this minimum pulse width for preset and clear applies for both global clear and array controls. the t lpa parameter must be added to this minimum width if the clear or reset signal incorporates the t lad parameter into the signal path. (3) this parameter is a guideline that is sample-tested only and is based on extensive device characterization. this parameter applies for both global and array clocking. (4) these parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each lab. (5) the f max values represent the highest frequency for pipelined data. (6) operating conditions: v ccio = 3.3 v 10 % for commercial and industrial use. (7) for epm7064s-5, epm7064s-6, epm7128s-6, epm7160s-6, epm7160s-7, epm7192s-7, and epm7256s-7 devices, these values are specified for a pia fan-out of one lab (16 macrocells). for each additional lab fan-out in these devices, add an additional 0.1 ns to the pia timing value. (8) the t lpa parameter must be added to the t lad , t lac , t ic , t en , t sexp , t acl , and t cppw parameters for macrocells running in the low-power mode. power consumption supply power (p) versus frequency ( f max in mhz) for max 7000 devices is calculated with the following equation: p = p int + p io = i cc int v cc + p io the p io value, which depends on the device output load characteristics and switching frequency, can be calculated using the guidelines given in application note 74 (evaluating power for altera devices) . the i ccint value, which depends on the switching frequency and the application logic, is calculated with the following equation: i ccint = a mc ton + b (mc dev ? mc ton ) + c mc used f max tog lc the parameters in this equation are shown below: mc ton = number of macrocells with the turbo bit option turned on, as reported in the max+plus ii report file ( .rpt ) mc dev = number of macrocells in the device mc used = total number of macrocells in the design, as reported in the max+plus ii report file ( .rpt ) f max = highest clock frequency to the device tog lc = average ratio of logic cells toggling at each clock (typically 0.125) a, b, c = constants, shown in table 36
altera corporation 51 max 7000 programmable logic device family data sheet this calculation provides an i cc estimate based on typical conditions using a pattern of a 16-bit, loadable, enabled, up/down counter in each lab with no output load. actual i cc values should be verified during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions. table 36. max 7000 i cc equation constants device a b c epm7032 1.87 0.52 0.144 epm7064 1.63 0.74 0.144 epm7096 1.63 0.74 0.144 epm7128e 1.17 0.54 0.096 epm7160e 1.17 0.54 0.096 epm7192e 1.17 0.54 0.096 epm7256e 1.17 0.54 0.096 epm7032s 0.93 0.40 0.040 epm7064s 0.93 0.40 0.040 epm7128s 0.93 0.40 0.040 epm7160s 0.93 0.40 0.040 epm7192s 0.93 0.40 0.040 epm7256s 0.93 0.40 0.040
52 altera corporation max 7000 programmable logic device family data sheet figure 14 shows typical supply current versus frequency for max 7000 devices. figure 14. i cc vs. frequency for max 7000 devices (part 1 of 2) frequency (mhz) epm7064 epm7032 0 50 frequency (mhz) 200 100 150 high speed 151.5 mhz 180 20 60 100 140 v cc = 5.0 v room temperature 0 50 200 100 150 low power 60.2 mhz 151.5 mhz 200 300 100 v cc = 5.0 v room temperature epm7096 05 0 frequency (mhz) 2 50 1 00 5 0 1 50 3 50 4 50 1 50 high speed v cc = 5.0 v room temperature low power typical i active (ma) cc typical i active (ma) cc typical i active (ma) cc 60.2 mhz 125 mhz 55.5 mhz high speed low power
altera corporation 53 max 7000 programmable logic device family data sheet figure 14. i cc vs. frequency for max 7000 devices (part 2 of 2) v cc = 5.0 v room temperature 0 frequency (mhz) 500 300 75 400 200 100 25 50 100 125 90.9 mhz 43.5 mhz epm7192e v cc = 5.0 v room temperature 0 frequency (mhz) 750 450 75 600 300 150 25 50 100 90.9 mhz 43.4 mhz epm7256e v cc = 5.0 v room temperature 0 frequency (mhz) 500 300 400 low power 200 100 50 100 100 mhz 47.6 mhz epm7160e 150 200 v cc = 5.0 v room temperature 0 frequency (mhz) 500 300 400 high speed 200 100 50 100 125 mhz 55.5 mhz epm7128e 150 200 high speed high speed high speed low power low power low power typical i active (ma) cc typical i active (ma) cc typical i active (ma) cc typical i active (ma) cc 125
54 altera corporation max 7000 programmable logic device family data sheet figure 15 shows typical supply current versus frequency for max 7000s devices. figure 15. i cc vs. frequency for max 7000s devices (part 1 of 2) v cc = 5.0 v room temperature 0 frequency (mhz) high speed low power 50 100 150 200 142.9 mhz 58.8 mhz epm7032s 10 20 30 40 50 60 v cc = 5.0 v room temperature 0 frequency (mhz) high speed low power 50 100 1 5 0 200 175.4 mhz 56.5 mhz epm7064s 20 40 60 80 100 120 v cc = 5.0 v room temperature 0 frequency (mhz) high speed low power 50 100 150 200 147.1 mhz 56.2 mhz e pm7128s 80 1 20 200 280 160 40 240 v cc = 5.0 v room temperature 0 frequency (mhz) high speed low power 50 100 1 5 0 200 149.3 mhz 56.5 mhz epm7160s 60 120 180 24 0 30 0 typical i active (ma) cc t ypical i a ctive (ma) cc typical i active (ma) cc t ypical i a ctive (ma) cc
altera corporation 55 max 7000 programmable logic device family data sheet figure 15. i cc vs. frequency for max 7000s devices (part 2 of 2) device pin-outs see the altera web site ( http://www.altera.com ) or the altera digital library for pin-out information. epm7192s v cc = 5.0 v room temperature 0 frequency (mhz) high speed low power 25 100 125 125.0 mhz 55.6 mhz 60 120 180 24 0 30 0 50 75 epm7256s v cc = 5.0 v room temperature 0 frequency (mhz) high speed low power 25 100 125 128.2 mhz 56.2 mhz 100 200 30 0 40 0 50 75 typical i active (ma) cc typical i active (ma) cc
56 altera corporation max 7000 programmable logic device family data sheet figures 16 through 22 show the package pin-out diagrams for max 7000 devices. figure 16. 44-pin package pin-out diagram package outlines not drawn to scale. notes: (1) the pin functions shown in parenthesis are only available in max 7000e and max 7000s devices. (2) jtag ports are available in max 7000s devices only. 44-pin plcc i/o i/o i/o vcc input/oe2/(gclk2) (1) input/gclrn input/oe1 input/gclk1 gnd i/o i/o i/o i/o/(tdo) (2 ) i/o i/o vcc i/o i/o i/o/(tck) (2) i/o gnd i/o i/o i/o i/o i/o gnd vcc i/o i/o i/o i/o i/o 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 epm7032 epm7032s epm7064 epm7064s (2) i/o /(tdi) i/o i/o gnd i/o i/o (2) i/o/(tms) i/o vcc i/o i/o 44-pin pqfp pin 12 pin 23 pin 34 pin 1 i/o i/o i/o vcc input/oe2/(gclk2) (1 ) input/gclrn input/oe1 input//gclk1 gnd i/o i/o i/o i/o/(tdo) (2) i/o i/o vcc i/o i/o i/o/(tck) (2) i/o gnd i/o i/o i/o i/o i/o gnd vcc i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o (2) i/o/(tms) i/o vcc i/o i/o epm7032 44-pin tqfp pin 12 pin 23 pin 34 pin 1 i/o i/o i/o vcc input/oe2/(gclk2) (1) input/gclrn input/oe1 input/gclk1 gnd i/o i/o i/o i/o/(tdo) (2) i/o i/o vcc i/o i/o i/o/(tck) (2) i/o gnd i/o i/o i/o i/o i/o gnd vcc i/o i/o i/o i/o i/o (2) i/o /(tdi) i/o i/o gnd i/o i/o (2) i/o /(tms) i/o vcc i/o i/o epm7032 epm7032s epm7064 epm7064s (2) i/o/(tdi)
altera corporation 57 max 7000 programmable logic device family data sheet figure 17. 68-pin package pin-out diagram package outlines not drawn to scale. notes: (1) the pin functions shown in parenthesis are only available in max 7000e and max 7000s devices. (2) jtag ports are available in max 7000s devices only. 68-pin plcc epm7064 epm7096 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 i/o i/o gnd i/o/(tdo) (2) i/o i/o i/o vccio i/o i/o i/o/(tck) (2) i/o gnd i/o i/o i/o i/o i/o vccio (2) i/o/(tdi) i/o i/o i/o gnd i/o i/o (2) i/o/(tms) i/o vccio i/o i/o i/o i/o gnd i/o i/o i/o gnd i/o i/o vccint input/oe2/(gclk2) (1 ) input/gclrn input/oe1 input/gclk1 gnd i/o i/o vccio i/o i/o i/o i/o i/o i/o vccio i/o i/o gnd vccint i/o i/o gnd i/o i/o i/o i/o vccio
58 altera corporation max 7000 programmable logic device family data sheet figure 18. 84-pin package pin-out diagram package outline not drawn to scale. notes: (1) pins 6, 39, 46, and 79 are no-connect (n.c.) pins on epm7096, epm7160e, and epm7160s devices. (2) the pin functions shown in parenthesis are only available in max 7000e and max 7000s devices. (3) jtag ports are available in max 7000s devices only. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 i/o vccio i/o/(tdi) (3) i/o i/o i/o i/o gnd i/o i/o i/o i/o/(tms) (3) i/o i/o vccio i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o gnd i/o (1) i/o i/o vccint input/oe2/(gclk2) (2) input/glcrn input/oe1 input/gclk1 gnd i/o i/o i/o (1) vccio i/o i/o i/o 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 i/o i/o gnd i/o/(tdo) (3) i/o i/o i/o i/o vccio i/o i/o i/o i/o/(tck) (3) i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vccio i/o (1) i/o i/o gnd vccint i/o i/o i/o (1) gnd i/o i/o i/o i/o i/o vccio 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 epm7064 epm7064s epm7096 epm7128e epm7128s epm7160e epm7160s 84-pin plcc
altera corporation 59 max 7000 programmable logic device family data sheet figure 19. 100-pin package pin-out diagram package outline not drawn to scale. figure 20. 160-pin package pin-out diagram package outline not drawn to scale. 100-pin pqfp pin 31 epm7064 epm7096 epm7128e epm7128s epm7160e pin 81 pin 1 pin 51 100-pin tqfp pin 1 pin 26 pin 7 6 pin 51 epm7064s epm7128s epm7160s pin 1 epm7128e epm7128s epm7160e epm7160s epm7192e epm7192s epm7256e pin 12 1 pin 81 pin 41 160-pin pga 160-pin pqfp r p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 epm7192e bottom view
60 altera corporation max 7000 programmable logic device family data sheet figure 21. 192-pin package pin-out diagram package outline not drawn to scale. figure 22. 208-pin package pin-out diagram package outline not drawn to scale. 192-pin pga epm7256e bottom view u t r p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 208-pin pqfp/rqfp pin 1 pin 15 7 pin 10 5 pin 53 epm7256e epm7256s
altera corporation 61 max 7000 programmable logic device family data sheet revision history the information contained in the max 7000 programmable logic device family data sheet version 6.5 supersedes information published in previous versions. the following changes were made in the max 7000 programmable logic device family data sheet version 6.5: version 6.5 the following changes were made in the max 7000 programmable logic device family data sheet version 6.5: updated text on page 16 . version 6.4 the following changes were made in the max 7000 programmable logic device family data sheet version 6.4: added note (5) on page 25 . version 6.3 the following changes were made in the max 7000 programmable logic device family data sheet version 6.3: updated the ?open-drain output option (max 7000s devices only)? section on page 18 .
copyright ? 2002 altera corporation. all rights reserved. altera, the programmable solutions company, th e stylized altera logo, specific device designations, and all other words and logos that are identified a s trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of alter a corporation in the u.s. and other countries. all other product or service names are the property of the ir respective holders. altera products are protected under numerous u.s. and foreign patents and pendin g applications, maskwork rights, and copyrights. altera warrants performance of its semiconductor products t o current specifications in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera corporation. altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services 1 01 innovation drive s an jose, ca 95134 ( 408) 544-7000 h ttp://www.altera.com a pplications hotline: ( 800) 800-epld c ustomer marketing: ( 408) 544-7104 l iterature services: l it_req@altera.com max 7000 programmable logic device family data sheet 62 altera corporation

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